1. Field of the Invention
The present invention relates to a semiconductor device and relates to a design method, an inspection method, and a design program therefor.
2. Description of the Related Art
FIG. 6 is a diagram showing an example of the layout for a semiconductor device, which is designed using a known automatic wiring tool. FIG. 7A is a diagram showing the wiring structure of area A1 in FIG. 6, and FIG. 7B is a sectional view along line J-J in FIG. 7A. FIG. 8A is a diagram showing the wiring structure of area A2 in FIG. 6, and FIG. 8B is a sectional view along line K-K in FIG. 8A.
In FIG. 6, reference numerals 100A to 100D indicate circuit blocks formed on a semiconductor substrate, and reference numerals 111 to 117 indicate wiring lines for connecting the circuit blocks 100A to 100D with each other. In the area A1 indicated by dashed lines, the wiring lines 111 to 113 extending in the horizontal direction on FIG. 6 intersect with the wiring lines 114 and 115 extending in the vertical direction on FIG. 6. In the area A2, the above wiring lines 114 and 115 intersect with the wiring line 117 extending in the horizontal direction on the figure, and this wiring line 117 is electrically connected to the wiring line 116 extending in the vertical direction on the figure.
As shown in FIG. 7A, the wiring lines 114 and 115 respectively have measurement electrodes 114b and 115b via extension wiring lines 114a and 115a, in a manner such that the areas of the measurement electrodes 114b and 115b do not overlap those of the wiring lines 111 to 113 in plan view.
In addition, in the wiring structure shown in FIGS. 8A and 8B, the wiring lines 114 and 115 are formed in the uppermost layer of the semiconductor device the wiring line 117 is formed between the third interlayer insulating film 103 and the second interlayer insulating film 102, and the wiring line 116 is formed between the second interlayer insulating film 102 and the first interlayer insulating film 101.
The wiring lines 116 and 117 are electrically connected to each other via a contact hole 105, which is formed through the second interlayer insulating film 102, at a position where the wiring lines 116 and 117 intersect with each other in plan view. In the uppermost layer above this intersection of the wiring lines 116 and 117, a measurement electrode 118 is formed, which is electrically connected to the wiring line 117 via a contact hole 106 formed through the third interlayer insulating film 103.
In conventional voltage or logic measurements for the inside of semiconductor devices, a thin metal needle is made to directly contact each wiring line on the surface of the semiconductor device, or secondary electrons obtained by irradiating the wiring line with an electron beam are measured. Typically, as shown in FIG. 7A, dedicated electrodes 114b and 115b for performing such a measurement are provided, and the measurement is performed via the electrodes 114b and 115b. However, in this case, each electrode is generally provided at a position which the designer believes necessary; thus, the results obtained by the automatic wiring layout tool should be manually corrected, thereby increasing labor (or man-hour). In addition, as shown in FIGS. 7A and 7B, space for forming the electrodes 114b and 115b and areas for providing the wiring lines 114a and 115a (for providing these electrodes) are also necessary.
However, in the above conventional methods of making a needle contact the wiring line or irradiating the wiring line with an electron beam, the wiring lines other than those provided in the uppermost layer cannot be measured. In order to perform the measurement for the wiring lines formed in the second or lower layers, a hole for measurement (here, the contact hole 106) is formed through the third interlayer insulating film 103 (see FIGS. 8A and 8B), so as to connect the electrode 118 to the wiring line 116, and the measurement is performed by making a probe 108 contact the electrode 118. However, in the semiconductor devices using the recent multilayer wiring technique, wiring lines are crowded and wiring density in the uppermost layer is very high; thus, it is very difficult to secure an area for providing such a measurement hole in the uppermost layer of the semiconductor device. Additionally, such an area for proving a measurement hole is manually searched for, thereby requiring a considerable amount of time.
In addition, Japanese Unexamined Patent Application. First Publication No. Sho 64-027241 discloses that a measurement terminal is provided in each unit cell of an electric circuit; however, in recent circuit design, the unit cell is generally covered with a wiring layer for a power supply or the like, and it is difficult to secure an area for providing the measurement terminal.
Japanese Unexamined Patent Application, First Publication No. Hei 9-139471 discloses using an automatic layout tool for measurement terminals; however, in the disclosed method, after completion of the wiring layout process, the layout operation is again performed by using a tool for searching for an area which satisfies specific conditions (i.e., an area where an electrode can be provided on the surface layer). In this case, if measurement terminals cannot be suitably arranged in the layout, correction of the entire design, such as reconsideration of the entire layout, is necessary. Therefore, increase in labor according to the increase in the load of simulation is inevitable, and thus it is difficult to put this method to practical use.
Japanese Unexamined Patent Application, First Publication No. Sho 62-076736discloses preparing cells in which a measurement terminal is mounted on a small-scale logic circuit, and performing connection between all cells after suitably arranging the cells in which no measurement terminal is mounted and the cells in which measurement terminals are mounted. However, in this case, each measurement terminal makes a pair with a logic circuit; thus, in the automatic wiring process, wiring cannot be produced in a layer above each circuit in the layout. In addition, the measurement terminal is not always mounted on each logic circuit (i.e., and each logic circuit in which the measurement terminal should be mounted is defined and selected; thus, it is difficult to automate the layout process.